Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2018833
date_generatedTue Nov 7 15:44:06 2017 os_platformWIN64
product_versionVivado v2017.3 (64-bit) project_idbf64a2ae585e4b0497ce31e8d14de554
project_iteration1 random_idd1d77fb6-854a-4edc-a07a-d67a5c51ed15
registration_id209824640_135109_210626508_205 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6500U CPU @ 2.50GHz cpu_speed2592 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 abstractsearchablepanel_show_search=3 addsrcwizard_specify_simulation_specific_hdl_files=1 basedialog_cancel=5
basedialog_close=2 basedialog_ok=43 basedialog_yes=1 cmdmsgdialog_ok=3
commandsinput_type_tcl_command_here=2 confirmsavetexteditsdialog_no=1 confirmsavetexteditsdialog_yes=1 coretreetablepanel_core_tree_table=8
createnewdiagramdialog_design_name=4 createsrcfiledialog_file_name=6 debugview_debug_cores_tree_table=3 debugwizard_sample_of_data_depth=1
defaultoptionpane_close=1 definemodulesdialog_architecture_name=4 definemodulesdialog_define_modules_and_specify_io_ports=5 definemodulesdialog_new_source_files=1
filesetpanel_file_set_panel_tree=136 filesetview_expand_all=1 flownavigatortreepanel_flow_navigator_tree=41 gettingstartedview_create_new_project=2
graphicalview_zoom_fit=14 hinputhandler_replace_text=3 languagetemplatesdialog_templates_tree=21 mainmenumgr_file=2
mainmenumgr_report=4 mainmenumgr_tools=10 mainmenumgr_window=10 msgtreepanel_message_view_tree=1
netlisttreeview_netlist_tree=2 pacommandnames_add_module_to_bd=7 pacommandnames_add_sources=8 pacommandnames_auto_connect_ports=9
pacommandnames_auto_update_hier=17 pacommandnames_create_top_hdl=3 pacommandnames_debug_window=1 pacommandnames_debug_wizard=1
pacommandnames_goto_netlist_design=1 pacommandnames_language_templates=4 pacommandnames_ports_window=1 pacommandnames_regenerate_layout=16
pacommandnames_save_design=2 pacommandnames_save_rsb_design=3 pacommandnames_set_as_top=5 pacommandnames_simulation_live_break=1
pacommandnames_simulation_live_restart=9 pacommandnames_simulation_live_run=31 pacommandnames_simulation_relaunch=4 pacommandnames_simulation_run_behavioral=4
pacommandnames_toggle_view_nav=1 pacommandnames_validate_rsb_design=6 pacommandnames_zoom_in=1 partchooser_boards=1
partchooser_parts=4 paviews_code=15 paviews_device=1 paviews_flow_navigator=1
paviews_project_summary=1 paviews_system=1 planaheadtab_refresh_changed_modules=6 planaheadtab_show_flow_navigator=1
progressdialog_background=1 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1 rdicommands_copy=1
rdicommands_custom_commands=6 rdicommands_delete=4 rdicommands_save_file=1 rdiviews_waveform_viewer=35
removesourcesdialog_also_delete=3 rsbapplyautomationbar_run_connection_automation=3 rsbexternalportproppanels_name=8 rungadget_show_warning_and_error_messages_in_messages=1
schematicview_regenerate=4 selectmenu_highlight=2 signaltreepanel_signal_tree_table=21 simulationliverunforcomp_specify_time_and_units=2
simulationobjectspanel_simulation_objects_tree_table=31 simulationscopespanel_simulate_scope_table=44 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1 srcchooserpanel_create_file=6
srcmenu_ip_hierarchy=18 systembuildermenu_add_ip=5 systembuildermenu_add_module=1 systembuildermenu_clear_debug=1
systembuildermenu_debug=5 systembuilderview_add_ip=2 systembuilderview_optimize_routing=3 taskbanner_close=2
waveformnametree_waveform_name_tree=15 waveformoptionsview_draw_waveform_shadow=4 waveformoptionsview_show_grid_lines=1 waveformoptionsview_show_signal_indices=6
waveformoptionsview_snap_to_transition=2 waveformview_goto_time_0=1 xpg_textfield_value_of_specified_parameter=3
java_command_handlers
addmoduletoblockdesign=7 addsources=8 autoconnectport=9 coreview=1
createblockdesign=4 createtophdl=3 customizersbblock=7 debugwizardcmdhandler=1
editcopy=1 editdelete=9 editundo=6 newproject=2
regeneratersblayout=16 runbitgen=1 runschematic=2 runsynthesis=2
savedesign=2 saversbdesign=3 settopnode=5 showview=4
simulationrelaunch=4 simulationrestart=9 simulationrun=4 simulationrunfortime=29
toggleviewnavigator=1 toolstemplates=4 validatersbdesign=6 viewlayoutcmd=1
viewtaskprojectmanager=3 viewtasksimulation=1 viewtasksynthesis=2 zoomin=2
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=3 export_simulation_ies=3
export_simulation_modelsim=3 export_simulation_questa=3 export_simulation_riviera=3 export_simulation_vcs=3
export_simulation_xsim=3 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=12 simulator_language=Mixed srcsetcount=6 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=5 totalsynthesisruns=5

unisim_transformation
post_unisim_transformation
bufg=2 dna_port=1 fdre=79 gnd=3
ibuf=2 lut1=1 lut2=4 lut3=2
lut4=2 lut5=1 lut6=5 mmcme2_adv=1
vcc=2
pre_unisim_transformation
bufg=2 dna_port=1 fdre=79 gnd=3
ibuf=2 lut1=1 lut2=4 lut3=2
lut4=2 lut5=1 lut6=5 mmcme2_adv=1
vcc=2

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=8 bram_ports_newly_gated=0 bram_ports_total=16 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2181 srls_augmented=0
srls_newly_gated=0 srls_total=232

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=4 numhdlrefblks=2 numhierblks=0 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=4 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VHDL x_iplibrary=BlockDiagram x_ipname=dna_reader_top
x_ipvendor=xilinx.com x_ipversion=1.00.a
clk_wiz_v5_4_2_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=dna_reader_top_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false
dna_port_wrapper/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VHDL
x_iplibrary=module_ref x_ipname=dna_port_wrapper x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
dna_reader_fsm/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VHDL
x_iplibrary=module_ref x_ipname=dna_reader_fsm x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
labtools_ila_v6_00_a/1
all_probe_same_mu=true all_probe_same_mu_cnt=1 c_adv_trigger=false c_data_depth=4096
c_en_strg_qual=false c_input_pipe_stages=0 c_num_of_probes=3 c_probe0_type=0
c_probe0_width=64 c_probe1_type=0 c_probe1_width=1 c_probe2_type=0
c_probe2_width=1 c_trigin_en=0 c_trigout_en=0 component_name=u_ila_0_CV
core_container=NA iptotal=1
labtools_xsdbm_v3_00_a/1
c_bscan_mode=false c_bscan_mode_with_core=false c_clk_input_freq_hz=300000000 c_en_bscanid_vec=false
c_enable_clk_divider=false c_num_bscan_master_ports=0 c_two_prim_mode=false c_use_ext_bscan=false
c_user_scan_chain=1 c_xsdb_num_slaves=1 component_name=dbg_hub_CV core_container=NA
iptotal=1
xlconstant_v1_1_3_xlconstant/1
const_val=0x0 const_width=1 core_container=NA iptotal=1
x_ipcorerevision=3 x_iplanguage=VHDL x_iplibrary=ip x_ipname=xlconstant
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
pdrc-190=16 xdcb-5=24

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.004147 clocks=0.005425
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.068992 die=xc7a35tcsg324-1 dsp_output_toggle=12.500000 dynamic=0.116414
effective_thetaja=4.8 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.000066 input_toggle=12.500000
junction_temp=25.9 (C) logic=0.000419 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.105688 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.185406 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=csg324 pct_clock_constrained=4.000000 pct_inputs_defined=50
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.000668
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=6.8 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=4.8 user_junc_temp=25.9 (C) user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.058541 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.012629 vccaux_total_current=0.071170 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000296 vccbram_static_current=0.000342 vccbram_total_current=0.000638 vccbram_voltage=1.000000
vccint_dynamic_current=0.010744 vccint_static_current=0.009918 vccint_total_current=0.020662 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000
version=2017.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=7.5 block_ram_tile_util_percentage=15.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=1.00
ramb18e1_only_used=1 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=7
ramb36_fifo_util_percentage=14.00 ramb36e1_only_used=7
primitives
bscane2_functional_category=Others bscane2_used=1 bufg_functional_category=Clock bufg_used=3
carry4_functional_category=CarryLogic carry4_used=45 dna_port_functional_category=Others dna_port_used=1
fdce_functional_category=Flop & Latch fdce_used=171 fdpe_functional_category=Flop & Latch fdpe_used=40
fdre_functional_category=Flop & Latch fdre_used=1952 fdse_functional_category=Flop & Latch fdse_used=18
ibuf_functional_category=IO ibuf_used=2 lut1_functional_category=LUT lut1_used=35
lut2_functional_category=LUT lut2_used=140 lut3_functional_category=LUT lut3_used=210
lut4_functional_category=LUT lut4_used=189 lut5_functional_category=LUT lut5_used=199
lut6_functional_category=LUT lut6_used=428 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=5 ramb18e1_functional_category=Block Memory ramb18e1_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=7 ramd32_functional_category=Distributed Memory ramd32_used=36
rams32_functional_category=Distributed Memory rams32_used=12 srl16e_functional_category=Distributed Memory srl16e_used=138
srlc16e_functional_category=Distributed Memory srlc16e_used=2 srlc32e_functional_category=Distributed Memory srlc32e_used=92
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=5 f7_muxes_util_percentage=0.03
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=1081 lut_as_logic_util_percentage=5.20 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=156 lut_as_memory_util_percentage=1.63 lut_as_shift_register_fixed=0 lut_as_shift_register_used=132
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=2181 register_as_flip_flop_util_percentage=5.24
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=1237 slice_luts_util_percentage=5.95
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=2181 slice_registers_util_percentage=5.24
fully_used_lut_ff_pairs_fixed=5.24 fully_used_lut_ff_pairs_used=91 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=1081 lut_as_logic_util_percentage=5.20
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=156 lut_as_memory_util_percentage=1.63
lut_as_shift_register_fixed=0 lut_as_shift_register_used=132 lut_ff_pairs_with_one_unused_flip_flop_fixed=132 lut_ff_pairs_with_one_unused_flip_flop_used=494
lut_ff_pairs_with_one_unused_lut_output_fixed=494 lut_ff_pairs_with_one_unused_lut_output_used=580 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=710 lut_flip_flop_pairs_util_percentage=3.41 slice_available=8150 slice_fixed=0
slice_used=666 slice_util_percentage=8.17 slicel_fixed=0 slicel_used=466
slicem_fixed=0 slicem_used=200 unique_control_sets_used=120 using_o5_and_o6_fixed=120
using_o5_and_o6_used=100 using_o5_output_only_fixed=100 using_o5_output_only_used=3 using_o6_output_only_fixed=3
using_o6_output_only_used=29
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=1 dna_port_util_percentage=100.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=1734490 bogomips=0 bram18=1 bram36=7
bufg=0 bufr=0 congestion_level=0 ctrls=120
dsp=0 effort=2 estimated_expansions=2101506 ff=2181
global_clocks=3 high_fanout_nets=1 iob=2 lut=1312
movable_instances=3977 nets=4251 pins=22875 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=top -verilog_define=default::[not_specified]
usage
elapsed=00:00:35s hls_ip=0 memory_gain=520.977MB memory_peak=820.660MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::