Видео-курсы VerificationAcademy :: Часть 1
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Sequential Logic Equivalence Checking
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О курсе
Sequential logic equivalence checking (SLEC) is effective in finding bugs in new logic required to reduce dynamic power consumption, validating last minute ECOs, or verifying that design optimizations aren’t too aggressive. It is also very efficient in verifying safety mechanisms used in ISO 26262 and other fault mitigating designs. SLEC’s effectiveness comes from using exhaustive formal verification algorithms, which do not require a testbench; and indeed are completely automated so the user does not need to know about formal technology themselves. Given the formal-based nature of the analysis, SLEC can prove functional equivalence of the two designs for all inputs and all time, or identify any differences between the two designs. In contrast, simulation-based approaches cannot prove sequential equivalence. Indeed, even with well-written constrained-random testbenches, simulation may find functional differences depending on the quality of the testbenches but such analysis could still miss critical corner cases. As such, SLEC can save a lot of resimulation time after small modifications of the design. In this course, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.
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SLEC Introduction
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SLEC for Design Optimization
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SLEC for Bug Fix / ECO
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SLEC for Low Power Clock Gating
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SLEC for Safety Mechanism
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UVM Basics
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О курсе
The UVM (Universal Verification Methodology) Basics course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The Verification Academy's goal for releasing the Basic UVM (Universal Verification Methodology) course is to raise the level of UVM (Universal Verification Methodology) knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption. This is not a substitute for hands-on language, methodology, or tool training. A working knowledge of VHDL or Verilog is recommended for the majority of this course-module and prior knowledge of SystemVerilog would be useful, but not required. You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy course.
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Introduction to UVM
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UVM "Hello World"
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Connecting Env to DUT
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Connecting Components
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Introducing Transactions
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Sequences and Tests
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Monitors and Subscribers
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Advanced UVM
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О курсе
The Advanced UVM (Universal Verification Methodology) module consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM course to take your UVM understanding to the next level. You will learn how to build tests and verification environments, understand how to use the factory and configuration database to customize your verification IP, and how to create reusable stimulus sequences, including for multi-layer protocols. We will also introduce the UVM Register layer, showing you how to create a register model and how to write and reuse register level tests. You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses, then the recommended prerequisite, Basic UVM.
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Architecting a UVM Testbench
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Understanding the Factory and Configuration
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Modeling Transactions
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How TLM Works
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The Proper Care and Feeding of Sequences
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Layered Sequences
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Writing and Managing Tests
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Setting Up the Register Layer
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Using the Register Layer
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Register-Based Testing
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Introduction to ISO 26262
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О курсе
The inclusion of complex electronic systems within vehicles continues to grow at an exponential pace. Ensuring these systems operate correctly and fail safely in the presence of hardware faults is of paramount importance in guaranteeing safety. ISO 26262 is the state of the art international standard defining the functional safety activities required in the development of electrical and electronic systems in production automobiles. Adherence to the standard provides unique challenges to companies who have previously developed automotive products as well as companies looking to enter into the automotive market. A holistic methodology across planning, design, and verification is critical in ensuring products meet safety requirements, deploy on time, and within budget. The purpose of this course is to provide engineers and managers with a basic understanding of the key concepts of ISO 26262. This includes information on the scope of the standard, how the standard addresses the broader automotive supply chain, and key requirements defined at each phase of the product lifecycle.
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ISO 26262 Creating an Optimal Safety Architecture
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ISO 26262 Fault Campaign Management
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ISO 26262 Bottoms-Up Safety Analysis
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ISO 26262 Requirements Management
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ISO 26262 in Simple Terms
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Portable Stimulus Basics
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О курсе
The new Portable Test and Stimulus Standard from Accellera provides the next leap in verification productivity needed to support the verification of our ever-growing system-on-chip (SoC) designs. In addition to increased complexity, SoC verification requires multiple platforms, including simulation, emulation and FPGA prototyping, each of which typically use different languages and formats for specifying the test, wasting precious time recreating the same test information throughout a project. Portable Stimulus addresses this problem by providing a single specification of test intent and coverage at a higher level of abstraction, allowing tools to generate target-specific implementations of the test for the desired platforms and freeing up the verification team to focus on what should be tested. In addition, Portable Stimulus also raises the level at which randomization can be applied, allowing many different but compatible scenarios to be generated from a single graph-based specification of test intent. This Verification Academy course will provide an introduction to the new Portable Test and Stimulus Standard, starting with a discussion of the need for and goals of the standard, taking the viewer through the actual standard itself to provide an understanding of how to create your own specification of Portable Stimulus and then showing how a tool can generate UVM, C or other implementations of the test for your required platform. We close by showing how you can get started today by importing your existing UVM code into Portable Stimulus.
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Why Portable Stimulus?
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Concepts & Language Introduction
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Test Realization
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Importing UVM into Portable Stimulus
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Introduction to DO-254
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О курсе
DO-254 has been around for over 15 years and has been applied almost exclusively in the commercial Aerospace industry. Because it has been focused in a subset of the electronic hardware market, many engineers and companies have little to no knowledge of DO-254. However, in recent years, the airplane manufacturers have sought to create or update aircraft with newer technology to make them more functional, efficient and safer. As a consequence of this initiative there are two challenges have come to the surface: Newer electronic components are being incorporated in airborne electronic hardware which were not used before. Consequently, a broader range electronic component vendors are being asked to provide or assist in documentation to support certification efforts. Engineering companies which design airborne electronic hardware are seeking to minimize cost and schedule of the development of hardware incorporating these electronic components with more functionality and more complexity. Some also incorporate new technology. The desire is to use advanced verification languages as well as advanced verification tools which are already being used in the commercial industry to address this. The purpose of this course is to provide engineers or technical leads with a basic understanding of the key concepts of DO-254. The hope is that with this information it will allow them to: Accurately assess the impact of how these challenges affect their ability to produce a hardware item that will meet criteria set forth in DO-254. Devise a solution to the challenges that will be compliant to guidance provided in DO-254.
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DO-254 in Simple Terms
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Planning for DO-254
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UVM Framework - One Bite at a Time
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О курсе
The UVM Framework is an open-source package that provides a reusable UVM methodology and code generator that provides rapid testbench generation. The sessions in this course describe the architecture, flow, generation, and use of UVM Framework testbenches.
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UVMF - Series Introduction
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UVMF - Overview
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Code Generation Introduction
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Agents: Architecture and Operation
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Interface Code Generation
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Environments: Architecture and Operation
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Scoreboards and Predictors
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Questa® VIP Integration
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Environment Code Generation
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Testbench: Architecture and Operation
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Bench Code Generation
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Instantiating the DUT
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Adding Tests and Sequences
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Sequence Categories
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UVMF & Emulation
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Running Simulations
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Code Generation Guidelines
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Stimulus and Analysis Data Flow
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Code Generation Merging
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Mathworks® Integration
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UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
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Handling Inconclusive Assertions in Formal Verification
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О курсе
Assertion-based formal verification can fully verify the functions of a design if all of the associated assertions can converge. Formal verification doesn’t need testbenches and can start much earlier in the process. It can consider all possible input stimulus sequences to find error traces of assertions or prove the assertions if no stimulus sequence can violate the assertions. The proof capability of formal doesn’t exist in simulation. More and more companies are adopting formal verification. However, due to the complexity of designs we have today, almost inevitably the user will encounter non-convergence problems which occur when the tools are unable to find either proofs or error traces for some assertions. Capacity limitations are a well-known characteristic of today’s formal verification tools. Fortunately, designers and verification engineers can learn methods for analyzing these non-convergence problems and improving their verification results. In this course, the instructor Jin Hou will introduce the techniques to help formal tools solve inconclusive assertions. She will show how to use tool options to help convergence, introduce techniques for reducing assertion and design complexity. She will also introduce advanced ND and DI techniques for reducing formal complexity, how to verify different functions separately, and bug hunting methods. Using these techniques, the user can get more results from formal tools.
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Editor Insight
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Easy Solutions
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Assertion Complexity Reduction
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Design Complexity Reduction
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Advanced Topic
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Inconclusive Debug Demo
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Formal Coverage
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О курсе
Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few. Like simulation, formal has metrics which can be used to determine when verification on a design block is complete. In one session we’ll compare simulation metrics to formal metrics and how the two can be combined as part of an overall verification flow leveraging the UCDB database and Verification Management analysis and tracking. Next, you will see how proof coverage can be used beyond the traditional coverage closure methods to improve your verification results. One session will focus on how proof coverage can be used to help debug vacuous assertions and uncoverable cover statements. Another session will focus on how proof coverage can be used to help debug inconclusive properties and some simple steps you can take based on this information. The final session will cover 2 important topics regarding formal coverage having to do with reachability, which can help with bounded proofs, along with over constraint analysis which is an important part of an assurance driven formal flow.
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Formal Coverage Introduction & Overview
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Formal Coverage vs. Simulation Coverage
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Formal Coverage for Property Debug
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Formal Coverage for Inconclusive Debug
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Formal for Over-Constraint and Reachability Analysis
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Property Debug Demo
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Formal Coverage Demo
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Inconclusive Debug Demo
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UVM Debug
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О курсе
Design complexity continues to increase, which is contributing to new challenges in verification and debug. Fortunately, new solutions and methodologies (such as UVM) have emerged to address growing design complexity. Yet, even with the productivity gains that can be achieved with the adoption of UVM, newer debugging challenges specifically related to UVM need to be addressed. In this course, we examine common UVM debug issues, and provide a systematic set of recommendations to effectively address them.
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UVM Debug Editor Insight
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UVM Connectivity Debug
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UVM Phase Debug
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Memory Leak Debug
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UVM Configuration Database Debug
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SystemVerilog OOP for UVM Verification
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О курсе
Object Oriented Programming (OOP), Design Patterns, and the UVM are technologies aimed at writing more manageable and re-usable code. Adopting these skills may seem like quite an overwhelming task as many hardware verification engineers do not have much of a software background. The SystemVerilog OOP for UVM Verification course is aimed at introducing the OOP features in SystemVerilog most commonly used by the UVM in the simplest form. No UVM is presented in this course, but the examples shown are directly applicable to the underlying principles that make the UVM work.
Upon completion of this course, you are encourage to view the Introduction to the UVM and the Basic UVM courses.
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Inheritance and Polymorphism
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OOP Design Pattern Examples
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An Introduction to Unit Testing with SVUnit
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О курсе
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates. This 5-part Verification Academy course establishes the case for unit testing design and testbench code with SVUnit. It goes on to demonstrate unit testing of modules and classes (including UVM components) through code demos and commentary. The course finishes with case studies that show the quality benefits developers can expect from unit testing with SVUnit.
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The Downside of Advanced Verification
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Introduction to SVUnit
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Your First Unit Test!
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Unit Testing UVM Components
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SVUnit Case Studies & Summary
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Power Aware CDC Verification
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О курсе
Reducing power consumption is essential to mobile and handheld application chips where reduced power contributes to longer battery life while minimally impacting performance. As more designs incorporate low power strategies, CDC errors are being found in the low power structures. Since low power logic is implemented late in the design cycle, these low power CDC issues are being missed by traditional CDC techniques.
CDC verification has become a mainstreamed tape out criteria. Design teams know that CDC verification is required to avoid metastability issues that result in reliability and functional problems in silicon. However, the low power design techniques are creating new CDC challenges that are not always addressed by traditional CDC methodologies and solutions. For example, leading-edge designs are now employing dynamic voltage and frequency scaling (DVFS) techniques that change the synchronous relationships between clocks. Now, designers must verify voltage domain crossing (VDC) paths in addition to the normal CDC paths. The additional challenge is that the power logic is not represented in the RTL design, but the power information is described in the unified power format (UPF) files. In the design flow, the power logic is not added until the implementation phase, but designers cannot wait until the implementation phase to complete the CDC analysis. Completing the CDC verification on the low power logic at the RTL design phase is critical to reducing the costs of identifying and fixing low power CDC issues.
In the process of helping project teams deploy power aware clock-domain crossing verification, we have discovered new CDC artifacts and developed new CDC techniques. This Verification Academy course describes the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.
You are encouraged to first view Clock-Domain Crossing Verification by Harry Foster that provides the basic CDC course.
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Power Aware CDC Introduction and Overview
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Understanding Low Power Impact on CDC Logic
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Describing Low Power Logic with UPF
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Integrating Power Aware CDC into a Design Flow
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Questa® CDC Power Aware Demo
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Getting Started with Formal-Based Technology
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О курсе
This course introduces basic concepts and terminology that should be useful by any engineer wishing to mature their formal-based technology skills. In addition, this course presents use models and guidelines for integrating formal property checking into a project’s verification flow.
Upcon completion of this course, you are encouraged to then view Formal-Based Technology: Automatic Formal Solutions and Formal Assertion-Based Verification.
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Formal Concepts and Solutions
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Formal Use Models and Organization Skills
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Formal Assertion-Based Verification
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О курсе
The automated formal apps reviewed in the “Automatic Formal Solutions” course have introduced a new generation of D&V engineers to the power of formal verification without the pain. This success has inspired renewed interest in creating formal testbenches for DUT-specific verification challenges that are well suited to formal. Specifically, formal tools statically analyze a design’s behavior with respect to a given set of properties, exhaustively exploring all possible input sequences in a breadth-first search manner to uncover design errors that would otherwise be missed.
In this course the instructors will show how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, how to setup the analysis for rapidly reaching a solution, and how to measure formal coverage and estimate whether you have enough assertions. Finally, a session on creating formal-based verification IP will show how to create libraries of reusable, optimized properties for formal analysis.
You are encouraged to first view Getting Started with Formal-Based Technology by Harry Foster that introduces basic concepts and terminology that should be useful by any engineer wishing to mature their formal-based technology skills.
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Introduction to Formal Assertion-Based Verification
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Basic Formal Closure, (Black Boxing and Cutpoint)
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PropCheck - Formal Model Checking
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Questa® PropCheck Demo
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