Видео-курсы VerificationAcademy :: Часть 2
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Formal-Based Technology: Automatic Formal Solutions
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О курсе
Even the most carefully designed UVM testbench is inherently incomplete since constrained-random methods can't hit every corner case. Unfortunately, this means that even after 100% functional coverage is achieved there can still be showstopper bugs hiding in unimagined state spaces. Hence, formal verification plays a vital role in the verification of today's complex designs. Formal tools statically analyze a design's behavior with respect to a given set of properties, exhaustively exploring all possible input sequences in a breadth-first search manner to uncover design errors that would otherwise be missed.
However, many engineers are concerned about having to learn assertion languages and formal techniques, or sharing the results from formal analysis in the context of the entire verification effort. Conversely, there are a series of verification problems that are well suited to formal analysis AND which can be automated using RTL and a corresponding specification of design intent (e.g. a UPF file for low power behavior, and IP-XACT description of control&status registers, etc.) These two factors have been the motivation behind the creation of a suite of "formal apps", defined as follows:
- A formal-based tool or well-documented methodology that's focused on a very specific, high-value verification challenge
- The given verification challenge is something that can be more efficiently solved using formal methods than using simulation-based approaches
- Finally, the need to create properties or have Assertion-Based Verification knowledge is significantly reduced or even completely eliminated – typically properties can be generated by the app automatically or are provided in a pre-packaged library
The benefits of the formal app approach are two-fold:
- First, users get to leverage the power of exhaustive formal algorithms without having to learn formal techniques
- The other key benefit is that because any engineer can use a formal app, you essentially get to use the best tool for the job. So if a given verification problem is easier and faster to solve with formal, you can now use formal instead of trying to force-fit simulation or some other method.
After a brief introductory session outlining the general architecture of formal apps, in each subsequent session of the course will deep dive on a specific verification challenge and the corresponding formal application.
You are encouraged to first view Getting Started with Formal-Based Technology by Harry Foster that introduces basic concepts and terminology that should be useful by any engineer wishing to mature their formal-based technology skills.
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Introduction to Automated Formal Apps
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AutoCheck - Push-Button Bug Hunting
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Questa® AutoCheck Demo
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Connectivity Check - Connectivity Verification Overview & Challenges
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Questa® Connectivity Check Demo
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CoverCheck - Accelerating Coverage Closure
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Questa® CoverCheck Demo
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Register Check - Memory Mapped Register Verification
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Questa® Register Check Demo
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SecureCheck - How Secure is your Design?
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Questa® SecureCheck Demo
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X-Check - Mitigating X Effects in Your Verification
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Questa® X-Check Demo
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Introduction to the UVM
Видео размещены здесь
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О курсе
The Introduction to the UVM (Universal Verification Methodology) course consists of twelve sessions that will guide you from rudimentary SystemVerilog through a complete UVM testbench. Each session is designed to give you the minimal amount of knowledge necessary to make it to the next level. Once you have worked through all these sessions, you will have experience with all the major components of the UVM as well as their concepts. You are then ready to learn more advanced techniques.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses. Upon completion of the Introduction to the UVM Course, you are encouraged to view Basic UVM and Advanced UVM.
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Overview and Welcome
- Overview and Welcome
- SystemVerilog Primer for VHDL Engineers
- Object Oriented Programming
- SystemVerilog Interfaces
- Packages, Includes and Macros
- UVM Components and Tests
- UVM Environments
- Connecting Objects
- Transaction Level Testing
- The Analysis Layer
- UVM Reporting
- Functional Coverage with Covergroups
- Introduction to Sequences
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Это еще не все материалы, перенос продолжается